As is known, in a floating gate nonvolatile memory cell storage of a logic state is carried out by programming the threshold voltage of the cell itself through the definition of the quantity of electrical charge stored in the floating gate region.
According to the information stored, memory cells may be distinguished into erased memory cells (logic state stored "1"), in which no electrical charge is stored in the floating gate region, and written or programmed memory cells (logic state stored "0"), in which an electrical charge is stored in the floating gate region that is sufficient to determine a sensible increase in the threshold voltage of the memory cell itself.
It is also known that reading of a memory cell consists in converting the current absorbed by the memory cell, at a given gate-source voltage, into a voltage which is then translated to a CMOS level at output from a special comparator circuit.
In particular, to carry out reading of a memory cell, a read voltage is supplied to the gate terminal of the cell which has a value comprised between the threshold voltage of an erased memory cell and that of a written memory cell, in such a way that, if the memory cell is written, the read voltage is lower than the threshold voltage, and hence no current flows in the cell, whereas, if the memory cell is erased, the read voltage is higher than the threshold voltage, and hence current flows in the cell.
Reading of a memory cell is carried out using a read circuit known as "sense amplifier", which, in addition to recognizing the logic state stored in the memory cell, also provides for the correct biasing of the drain terminal of the memory cell. During the read phase, the drain terminal of a memory cell is in fact biased with a voltage of approximately 1 V, which is obtained as a compromise between a maximum value that is not to be exceeded in order to avoid the so-called "soft writing" phenomenon, i.e., spurious writing of the memory cell during reading of the same, and a minimum value, below which the intensity of the current flowing in the memory cell is excessively small and would require, on the one hand, the use of an extremely precise sense amplifier, and thus one more complex and costly, in order to carry out correct reading of the logic state stored in the cell, and further would usually lead to a degradation in performance in terms of reading speed.
In order to provide an example, FIG. 1 shows the output characteristics I.sub.DS =f(V.sub.GS) of a memory cell, which link the gate-source voltage V.sub.GS to the drain-source current I.sub.DS of a memory cell, for values of the voltage VD of the drain terminal of the memory cell of 1 V, 0.8 V and 0.5 V, and in which it is evident that as the voltage V.sub.D of the drain terminal of the memory cell decreases, there is a corresponding decrease in the drain-source current I.sub.DS flowing in the memory cell, given the same gate-source voltage V.sub.GS.
FIG. 2 shows one of the classic circuit diagrams of a sense amplifier, in which, for reasons of simplicity, the column decoding, which enables a single column of the memory array to be selected at a time, has been omitted.
According to what is illustrated in the above-mentioned figure, the sense amplifier, indicated as a whole by 1, comprises a supply line 2 set at a supply voltage V.sub.CC (for example, between 2.5 and 3.8 V), a ground line 3 set at the ground voltage V.sub.GND (for example, 0 V), an array branch 4 connected, via an array bit line 5, to an array cell 6, the content of which is to be read, and a reference branch 8 connected, via a reference bit line 10, to a reference cell 11, the content of which is known.
In particular, the array cell 6 and the reference cell 11 have gate terminals receiving the same read signal V.sub.READ, drain terminals connected to the array bit line 5 and, respectively, to the reference bit line 10, and source terminals connected to the ground line 3.
The array branch 4 comprises an array biasing stage 12 for biasing the drain terminal of the array cell 6, comprising a fedback cascode structure formed of an NMOS transistor 14 and a NOR logic gate 20. In particular, the NMOS transistor 14 has a source terminal connected to the array bit line 5, a drain terminal connected, via a diode-connected PMOS transistor 16, to the supply line 2, and a gate terminal connected to an output terminal of the NOR logic gate 20, which in turn has a first input terminal receiving a control signal ENS and a second terminal connected to the source terminal of the NMOS transistor 14.
The control signal ENS is a logic signal, the low logic level of which enables operation of the sense amplifier 1, whilst its high logic level disables operation of the sense amplifier 1.
The reference branch 8 comprises a reference biasing stage 21 for biasing the drain terminal of the reference cell 11, comprising an NMOS transistor 22 having a source terminal connected to the reference bit line 10, a drain terminal connected, via a PMOS transistor 24, to the supply line 2, and a gate terminal connected to an output terminal of a NOR logic gate 26, which has a first input terminal receiving the control signal ENS and a second terminal connected to the source terminal of the NMOS transistor 22.
The PMOS transistors 16, 24 form a current mirror 28 carrying out the aforementioned current-to-voltage conversion, and in particular have gate terminals connected together and to the drain terminal of the PMOS transistor 16, source terminals connected to the supply line 2, and drain terminals connected to the drain terminals of the NMOS transistor 14 and, respectively, of the NMOS transistor 22 and defining an array node 30 and a reference node 32, respectively.
Finally, the sense amplifier 1 comprises a comparator 34 having a non-inverting input terminal connected to the array node 30, an inverting input terminal connected to the reference node 32, and an output terminal on which a logic signal is supplied that is indicative of the logic state stored in the array cell 6.
Connected to the array bit line 5 are moreover a number of array cells 6 arranged on the same array column, the capacitances of which are represented schematically in FIG. 1 by a equivalent array capacitor 36.
As shown in greater detail in FIG. 3, each NOR gate 20, 26 comprises an inverter 40 formed of a pull down NMOS transistor 42 and a pull up PMOS transistor 44 having gate terminals connected together and to the source terminals of the NMOS transistors 14 and 22, respectively, and drain terminals connected together and to the gate terminals of the NMOS transistors 14 and 22, respectively. The NMOS transistor 42 further has a source terminal connected to ground, whilst the PMOS transistor 44 has a source terminal connected to a drain terminal of a PMOS transistor 46 having a source terminal connected to the supply line 2 and a gate terminal receiving the control signal ENS.
Finally, each NOR logic gate 20, 26 comprises an NMOS transistor 48 having a gate terminal receiving the control signal ENS, a source terminal connected to ground, and the drain terminal connected to the drain terminals of the NMOS transistor 42 and the PMOS transistor 44.
The NOR logic gate 20 drives in feedback the NMOS transistor 14, which operates in cascode configuration, performing the following three different functions.
The first function performed by the NMOS transistor 14 is that of decoupling the array node 30 from the array bit line 5, and this has positive effects on the reading speed. In fact, the capacitance of the equivalent array capacitor 36 depends upon the parameters of the technological process and upon the type of architecture of the memory array, and, in any case, it is of several pF as compared to the tens of fF of the array node 30. Thanks to the cascode effect, the variation in the voltage present on the array node 36 and produced by the current I.sub.MAT flowing in the array bit line 5 is higher than that present across the equivalent array capacitor 30 and produced by the same current, and since the voltage present between the array node 30 and the reference node 32 constitutes the input voltage of the comparator 34, it may be readily understood how this aspect is particularly important for the reading speed.
The second function performed by the NMOS transistor 14 is that of preventing the PMOS transistor 16 from altering the biasing of the array bit line 5. This effect is obtained thanks to the high output impedance of the NMOS transistor 14 due to the cascode effect.
Finally, the third function performed by the NMOS transistor 14 is that of preventing the soft writing phenomenon. In fact, as soon as the array bit line 5 exceeds the logic threshold of the NOR logic gate 20, the latter reduces the voltage of the gate terminal of the NMOS transistor 14, thus interrupting the conductive path through which the array bit line 5 itself is charged and preventing the drain terminal of the array cell 6 from exceeding the logic threshold of the NOR logic gate 20.
The presence of a NOR logic gate 20 instead of a simple inverter is justified by the possibility of turning off the sense amplifier 1 whenever required (during programming, during stand by, etc.), the latter being on when the control signal ENS supplied to the input terminals of the NOR logic gates 20, 26 goes low.
In particular, the soft writing problem especially affects the reference cells 11 used for reading, in that these are biased whenever any memory location is to be read. It should be borne in mind that, typically, raising the voltage of the drain terminal of a memory cell by 100 mV above 1 V means decreasing the service life of the memory device by one order of magnitude; i.e., in other words, it means that, in the event of the shifting of the thresholds of the reference cells 11, the memory device may malfunction after one year of activity instead of after ten years.
The requisites, in terms of reliability of reading the contents of memory cells and, consequently, in terms of precise biasing of the drain terminals of the memory cells to be read, have become increasingly stringent ever since technological processes imposed a reduction in the gain of memory cells and ever since multilevel nonvolatile memories, i.e., ones formed of memory cells able to store more than one bit each, began appearing on the market.
The introduction of this type of memories has, in fact, revealed more clearly the intrinsic limits of known sense amplifiers, by means of which it is altogether impossible to meet the requirements for correct biasing of the drain terminal.
As is known, in fact, programming of memory cells is affected by uncertainty, and the memory cells in which the same item of information is stored do not all present the same threshold voltage but, in practice, to each item of information to be stored is associated a respective distribution of the values of the respective threshold voltage, these values being comprised between a minimum value and a maximum value set apart from the maximum value of the previous distribution and/or from the minimum value of the subsequent distribution in a way sufficient for enabling correct reading of the cells, the reading consisting in converting the current flowing in the memory cell to be read into a voltage, which is then compared with different voltage values intermediate between the threshold distributions referred to above.
FIGS. 4 and 5 show examples of the distributions of the threshold voltages V.sub.t associated, respectively, to a two level conventional memory cell, i.e., a memory cell in which only one bit is stored, and a four level memory cell, i.e., a memory cell in which two bits are stored. For each distribution, the maximum and minimum values typical of the threshold voltages V.sub.t and the binary information associated thereto are moreover indicated on a non uniform scale. Of course, other threshold voltages can be used and many more bits than two stored in some memory cells.
From a simple analysis of the above figures, it is immediately evident that, within the same range of threshold voltages, the use of multilevel memory cells means having four distributions instead of two, and that thus the use of multilevel memory cells involves a reduction in the distance between two adjacent distributions, to which there corresponds a reduction in the difference between the currents that flow in the memory cells themselves and that correspond to adjacent levels. Typically, between two adjacent distributions, the corresponding difference between the currents flowing in the memory cells is in the region 20 .mu.A.
Consequently, in the case of use of memory cells with two bits per cell, the sense amplifier 1 has to work with as many as four distributions, and no longer two as in the case of conventional memory cells, and consequently the reliability requisites become more stringent, in that the distributions are closer together and the current used to carry out reading is lower.
It is therefore evident how the correct and precise biasing of the drain terminal of the memory cell 6 during the read phase is extremely important.
The sense amplifier 1 illustrated in FIG. 1 does not guarantee, however, precision in the biasing of the drain terminals of the memory cells to be read that is sufficient for meeting the reliability requisites imposed by the advent of multilevel memory cells.
In fact, typically, with the present fabrication processes, the threshold voltage of the memory cell is between 700 and 800 mV, and since the logic threshold of the NOR logic gate 20 must be 1 V, the NOR logic gate 20 itself is sized using a PMOS transistor 44 having a mainly resistive behavior and an NMOS transistor 42 having a mainly conductive behavior. In this way, the logic threshold of the NOR logic gate 20 is close to that of the NMOS transistor 42; i.e., in other words, the NOR logic gate 20 is unbalanced in favor of the NMOS transistor 42.
In actual fact, the NOR logic gate 20 goes into action only when the NMOS transistor 42 is on and its own logic threshold is higher than that of the NMOS transistor 42. Basically, the voltage of the drain terminal of the array cell 6 to be read is substantially equal to the threshold voltage of the NMOS transistor 42 increased by a quantity necessary for operating the NOR logic gate 20 itself.
A large number of the devices currently available on the market implement the solution described above to obtain the 1 V voltage on the drain terminal of the memory cell to be read.
A regulation based on the use of an NMOS transistor 14 operating as cascode and a NOR logic gate 20 markedly unbalanced is, however, affected to a considerable extent by variations in the supply voltage and in the temperature, which at present range, respectively, between 2.5 and 3.8 V and -40 and +120.degree. C.
FIG. 6 shows the pattern of the voltage V.sub.D of the drain terminal of an array cell 6 to be read, in which the binary information "00" is stored, as a function of the supply voltage V.sub.CC and for temperature values of 40.degree.C., 27.degree. C. and 90.degree. C. As may be noted, the voltage V.sub.D increases, given the same temperature T, as the supply voltage V.sub.CC increases, and, given the same supply voltage V.sub.CC, as the temperature T decreases.
The effect of the variation in the supply voltage V.sub.CC on the markedly unbalanced NOR logic gate 20 may be explained as follows: assuming that we are working with supply voltages V.sub.CC of 2.5 V and we set the voltage V.sub.D exactly at 1 V, the PMOS transistor 44 and NMOS transistor 42 are sized so that, as has been said above, the NOR logic gate 20 is unbalanced in favor of the NMOS transistor 42. However, when the supply voltage V.sub.CC increases to 3.8 V, the gate-source voltage of the PMOS transistor 44 increases by 1.3 V, whilst the gate-source voltage of the NMOS transistor 42 increases by a few tens of mV, as may be deduced from an analysis of FIG. 6. It is as if, on account of the increase in the supply voltage V.sub.CC, the "force" of the PMOS transistor 44 were increased, and it is for this reason that the unbalanced NOR gate 20 tends to draw the drain terminal of the array cell 6 towards higher voltages as the supply voltage V.sub.CC increases. Similar considerations may be made as regards the effect of the variation in temperature on the unbalanced NOR logic gate 26.
Since at present the supply voltage V.sub.CC and the temperature T range, respectively, between 2.5 and 3.8 V and between -40 and +120.degree. C., and since the voltage V.sub.D of the drain terminal of the array cell 6 to be read must not under any circumstances exceed 1 V, it is necessary to size the sense amplifier 1 so as to have the voltage V.sub.D of 1 V in the worst operating case, i.e., with a supply voltage of 3.8 V and an operating temperature of -40 .degree. C.
In this way, however, when the supply voltage V.sub.CC is 2.5 V and the temperature T is 120.degree. C., the drain terminal of the array cell 6 to be read is set at a voltage V.sub.D well below 1 V, namely 0.7 V, with a variation of as much as 300 V. In general, this entails, in conventional memory cells, a degradation in performance in terms of reading speed, and, in multilevel memory cells, even the impairment of the functioning of the entire memory device.